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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ade7759 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 active energy metering ic with di/dt sensor interface functional block diagram avdd reset dvdd dgnd zx sag cf v1p v1n v2n v2p temp sensor adc adc dfc ade7759 apos[15:0] lpf2 multiplier integrator multiplier clkin clkout din dout sclkref in/out cs irq agnd apgain[11:0] dt registers and serial interface cfnum[11:0] cfden[11:0] 2.4v reference 4k phcal[7:0] hpf1 lpf1 features high accuracy, supports iec 687/1036 on-chip digital integrator allows direct interface with current sensors with di/dt output such as rogowski coil less than 0.1% error over a dynamic range of 1000 to 1 on-chip user-programmable threshold for line voltage sag detection and psu supervisory the ade7759 supplies sampled waveform data and active energy (40 bits) digital power, phase and input dc offset calibration on-chip temperature sensor (typical 1 lsb/ c resolution) spi-compatible serial interface pulse output with programmable frequency interrupt request pin (irq) and irq status register proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time reference 2.4 v 8% (20 ppm/ c typical) with external overdrive capability single 5 v supply, low power consumption (25 m w typical) general description the ade7759 is an accurate active power and energy measurement ic with a serial interface and a pulse output. the ade7759 incor- porates two second order - ? adcs, a digital integrator (on ch1), reference circuitry, temperature sensor, and all the signal processing required to perform active power and energy measurement. an on-chip digital integrator allows direct interface to di/dt current sensors such as a rogowski coil. the digital integrator eliminates the need for an external analog integrator and pro- vides excellent long-term stability and precise phase matching between the current and the voltage channels. the integrator can be switched off if the ade7759 is used with conventional current sensors. the ade7759 contains a sampled waveform register and an active energy register capable of holding at least 11.53 seconds of accumu- lated power at full ac load. data is read from the ade7759 via the serial interface. the ade7759 also provides a pulse output (cf) with frequency that is proportional to the active power. in addition to active power information, the ade7759 also provides various system calibration features, i.e., channel offset correction, phase calibration, and power offset correction. the part also incorporates a detection circuit for short duration voltage drop (sag). the voltage threshold and the duration (in number of half-line cycles) of the drop are user programmable. an open drain logic output ( sag ) goes active low when a sag event oc curs. a zero crossing output (zx) produces an output that is synchro- nized to the zero crossing point of the line voltage. this output can be used to extract timing or frequency information from the line. the signal is also used internally to the chip in the line cycle energy accumulation mode; i.e., the number of half-line cycles in which the energy accumulation occurs can be con- trolled. line cycle energy accumulation enables a faster and more precise energy accumulation and is especially useful dur- ing calibration. this signal is also useful for synchronization of relay switching with a voltage zero crossing. the interrupt request output is an open drain, active low logic output. the interrupt status register indicates the nature of the interrupt, and the interrupt enable register controls which event produces an output on the irq pin. the ade7759 is available in a 20-lead ssop package. * u.s. patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
rev. 0 ade7759 C2C table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 timing characteristics . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin function descriptions . . . . . . . . . . . . . . . . . . 7 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 measurement error . . . . . . . . . . . . . . . . . . . . . . . . . 8 phase error between channels . . . . . . . . . . . . . 8 power supply rejection . . . . . . . . . . . . . . . . . . . . . . 8 adc offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 gain error match . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical performance characteristics (tpc) . . 9 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 di/dt current sensor and digital integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 zero crossing detection . . . . . . . . . . . . . . . . . . . 13 line voltage sag detection . . . . . . . . . . . . . . . . 14 sag level set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power supply monitor . . . . . . . . . . . . . . . . . . . . . . 14 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 using the ade7759 interrupts with an mcu . . . . . . . . . 15 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 temperature measurement . . . . . . . . . . . . . . . . 16 analog-to-digital conversion . . . . . . . . . . . . . 16 antialias filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reference circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 channel 1 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 channel 1 adc gain adjust . . . . . . . . . . . . . . . . . . . . . . 18 channel 1 sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 channel 1 and channel 2 waveform sampling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 channel 2 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 channel 2 sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . 19 active power calculation . . . . . . . . . . . . . . . . . 20 energy calculation . . . . . . . . . . . . . . . . . . . . . . . . 21 integration time under steady load . . . . . . . . . . . . . . . . 22 power offset calibration . . . . . . . . . . . . . . . . . . 22 energy-to-frequency conversion . . . . . . . . . 22 line cycle energy accumulation mode . . . 24 calibrating the energy meter . . . . . . . . . . . . . 24 calculating the average active power . . . . . . . . . . . . . . . 24 calibrating the frequency at cf . . . . . . . . . . . . . . . . . . . 25 energy meter display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 clkin frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 suspending the ade7759 functionality . . . . 26 application information . . . . . . . . . . . . . . . . . . . 26 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 serial write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 serial read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 checksum register . . . . . . . . . . . . . . . . . . . . . . . . . 28 register descriptions . . . . . . . . . . . . . . . . . . . . . . 29 communications register . . . . . . . . . . . . . . . . . . . . . . . . 29 mode register (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 interrupt status register (04h) . . . . . . . . . . . . . . . . . . . . 31 reset interrupt status register (05h) . . . . . . . . . . . . . . . 31 ch1os register (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 32
rev. 0 C3C ade7759 specifications 1 parameter spec unit test conditions/comments energy measurement accuracy measurement bandwidth 14 khz clkin = 3.579545 mhz measurement error 1 on channel 1 channel 2 = 300 mv rms/60 hz, gain = 1 channel 1 range = 0.5 v full-scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.1 % typ over a dynamic range 1000 to 1 gain = 8 0.1 % typ over a dynamic range 1000 to 1 gain = 16 0.2 % typ over a dynamic range 1000 to 1 channel 1 range = 0.25 v full-scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.1 % typ over a dynamic range 1000 to 1 gain = 8 0.2 % typ over a dynamic range 1000 to 1 gain = 16 0.2 % typ over a dynamic range 1000 to 1 channel 1 range = 0.125 v full-scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.2 % typ over a dynamic range 1000 to 1 gain = 8 0.2 % typ over a dynamic range 1000 to 1 gain = 16 0.4 % typ over a dynamic range 1000 to 1 phase error 1 between channels 0.05 max line frequency = 45 hz to 65 hz, hpf on ac power supply rejection 1 av dd = dv dd = 5 v + 175 mv rms/120 hz output frequency variation (cf) 0.2 % typ channel 1 = 20 mv rms/60 hz, gain = 16, range = 0.5 v channel 2 = 300 mv rms/60 hz, gain = 1 dc power supply rejection 1 av dd = dv dd = 5 v 250 mv dc output frequency variation (cf) 0.3 % typ channel 1 = 20 mv rms/60 hz, gain = 16, range = 0.5 v channel 2 = 300 mv rms/60 hz, gain = 1 analog inputs see analog inputs section maximum signal levels 0.5 v max v1p, v1n, v2n, and v2p to agnd input impedance (dc) 390 k ? min bandwidth 14 khz clkin/256, clkin = 3.579545 mhz gain error 1, 3 external 2.5 v reference, gain = 1 on channel 1 and 2 channel 1 range = 0.5 v full-scale 4 % typ v1 = 0.5 v dc range = 0.25 v full-scale 4 % typ v1 = 0.25 v dc range = 0.125 v full-scale 4 % typ v1 = 0.125 v dc channel 2 4 % typ v2 = 0.5 v dc gain error match 1 external 2.5 v reference channel 1 range = 0.5 v full-scale 0.3 % typ gain = 1, 2, 4, 8, 16 range = 0.25 v full-scale 0.3 % typ gain = 1, 2, 4, 8, 16 range = 0.125 v full-scale 0.3 % typ gain = 1, 2, 4, 8, 16 channel 2 0.3 % typ gain = 1, 2, 4, 8, 16 offset error 1 channel 1 10 mv max gain = 1 channel 2 10 mv max gain = 1 waveform sampling sampling clkin/128, 3.579545 mhz/128 = 27.9 ksps channel 1 see channel 1 sampling signal-to-noise plus distortion 62 db typ 150 mv rms/60 hz, range = 0.5 v, gain = 2 bandwidth (C3 db) 14 khz clkin = 3.579545 mhz channel 2 see channel 2 sampling signal-to-noise plus distortion 52 db typ 150 mv rms/60 hz, gain = 2 bandwidth (C3 db) 156 hz clkin = 3.579545 mhz (av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.579545 mhz xtal, t min to t max = ?0 c to +85 c unless otherwise noted.)
rev. 0 C4C ade7759?pecifications parameter spec unit test conditions/comments reference input ref in/out input voltage range 2.6 v max 2.4 v + 8% 2.2 v min 2.4 v C 8% input capacitance 10 pf max on-chip reference nominal 2.4 v at ref in/out pin reference error 200 mv max current source 10 a max output impedance 4 k ? min temperature coefficient 20 ppm/ c typ clkin note all specifications clkin of 3.579545 mhz input clock frequency 4 mhz max 1 mhz min logic inputs reset , din, sclk, clkin, and cs input high voltage, v inh 2.4 v min dv dd = 5 v 5% input low voltage, v inl 0.8 v max dv dd = 5 v 5% input current, i in 3 a max typically 10 na, v in = 0 v to dv dd input capacitance, c in 10 pf max logic outputs sag and irq open drain outputs, 10 k ? pull-up resistor output high voltage, v oh 4v mini source = 5 ma output low voltage, v ol 0.4 v max i sink = 0.8 ma zx and dout output high voltage, v oh 4v mini source = 5 ma output low voltage, v ol 0.4 v max i sink = 0.8 ma cf output high voltage, v oh 4v mini source = 5 ma output low voltage, v ol 1v maxi sink = 7 ma power supply for specified performance av dd 4.75 v min 5 v C 5% 5.25 v max 5 v + 5% dv dd 4.75 v min 5 v C 5% 5.25 v max 5 v + 5% ai dd 3 ma max typically 2.0 ma di dd 4 ma max typically 3.0 ma notes 1 see terminology section for explanation of specifications. 2 see plots in typical performance characteristics. 3 see analog inputs section. specifications subject to change without notice. (continued)
rev. 0 ade7759 C5C timing characteristics 1, 2 parameter a, b versions unit test conditions/comments write timing t 1 20 ns (min) cs falling edge to first sclk falling edge t 2 150 ns (min) sclk logic high pulsewidth t 3 150 ns (min) sclk logic low pulsewidth t 4 10 ns (min) valid data setup time before falling edge of sclk t 5 5 ns (min) data hold time after sclk falling edge t 6 6.4 s (min) minimum time between the end of data byte transfers t 7 4 s (min) minimum time between byte transfers during a serial write t 8 100 ns (min) cs hold time after sclk falling edge read timing t 9 4 s (min) minimum time between read command (i.e., a write to communications register) and data read t 10 4 s (min) minimum time between data byte transfers during a multibyte read t 11 3 30 ns (min) data access time after sclk rising edge following a write to the communi- cations register t 12 4 100 ns (max) bus relinquish time after falling edge of sclk 10 ns (min) t 13 4 100 ns (max) bus relinquish time after rising edge of cs 10 ns (min) notes 1 sample tested during initial release and after any redesign or process change that may affect this parameter. all input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 v. 2 see figures 2 and 3 and serial interface section of this data sheet. 3 measured with the load circuit in figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 4 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit in figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time quoted in the timing characterist ics is the true bus relinquish time of the part and is independent of the bus loading. (av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.579545 mhz xtal, t min to t max = ?0 c to +85 c unless otherwise noted.) t 7 t 5 t 4 cs sclk din a4 a3 a2 a1 a0 db7 most significant byte 1 db0 db7 db0 least significant byte 00 command byte t 1 t 2 t 3 t 6 t 7 t 8 figure 2. serial write timing cs sclk din a4 a3 a2 a1 a0 000 t 1 t 10 dout db7 most significant byte least significant byte command byte db0 db7 db0 t 13 t 12 t 9 t 11 t 11 figure 3. serial read timing to output pin 2.1v 1.6ma i oh i ol 200 a c l 50pf figure 1. load circuit for timing specifications
rev. 0 ade7759 C6C absolute maximum ratings * (t a = 25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to av dd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v analog input voltage to agnd v 1p , v 1n , v 2p , and v 2n . . . . . . . . . . . . . . . . . C6 v to +6 v reference input voltage to agnd . . C0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . C0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . C0.3 v to dv dd + 0.3 v operating temperature range industrial (a, b versions) . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c 20-lead ssop, power dissipation . . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 112 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ade7759 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model package option * ade7759ars rs-20 ade7759arsrl rs-20 EVAL-ADE7759E ade7759 evaluation board *rs = shrink small outline package in tubes; rsrl = shrink small outline package in reel.
rev. 0 C7C ade7759 pin function descriptions pin no. mnemonic description 1 reset reset pin for the ade7759. a logic low on this pin will hold the adcs and digital circuitry (including the serial interface) in a reset condition. 2dv dd digital power supply. this pin provides the supply voltage for the digital circuitry in the ade7759. the supply voltage should be maintained at 5 v 5% for specified operation. this pin should be decoupled to dgnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 3av dd analog power supply. this pin provides the supply voltage for the analog circuitry in the ade7759. the supply should be maintained at 5 v 5% for specified operation. every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling method. this pin should be decoupled to agnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 4, 5 v1p, v1n analog inputs for channel 1. this channel is intended for use with the di/dt current transducers such as rogowski coil, or other current sensors such as shunt or current transformer (ct). these inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 v, 0.25 v and 0.125 v, depending on the full scale selectionsee analog inputs section. channel 1 also has a pga with gain selections of 1, 2, 4, 8, or 16. the maximum signal level at these pins with respect to agnd is 0.5 v. both inputs have internal esd protection circuitry. in addition, an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 6, 7 v2n, v2p analog inputs for channel 2. this channel is intended for use with the voltage transducer. these inputs are fully differential voltage inputs with a maximum differential signal level of 0.5 v. channel 2 also has a pga with gain selections of 1, 2, 4, 8, or 16. the maximum signal level at these pins with respect to agnd is 0.5 v. both inputs have internal esd protection circuitry, and an over- voltage of 6 v can be sustained on these inputs without risk of permanent damage. 8 agnd this pin provides the ground reference for the analog circuitry in the ade7759, i.e., adcs and reference. this pin should be tied to the analog ground plane or the quietest ground reference in the system. this quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. in order to keep ground noise around the ade7759 to a minimum, the quiet ground plane should be connected to the digital ground plane at only one point. it is acceptable to place the entire device on the analog ground planesee application information section. 9 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 2.4 v 8% and a typical temperature coefficient of 20 ppm/ c. an external reference source may be connected at this pin. in either case this pin should be decoupled to agnd with a 1 f capacitor in parallel with a 100 nf capacitor. 10 dgnd this provides the ground reference for the digital circuitry in the ade7759, i.e., multiplier, filters, and frequency output (cf). because the digital return currents in the ade7759 are small, it is acceptable to connect this pin to the analog ground plane of the systemsee application information section. however, high bus capacitance on the dout pin may result in noisy digital current that affects performance. 11 cf calibration frequency logic output. the cf logic output gives active power information. this output is intended to be used for operational and calibration purposes. the full-scale output fre- quency can be adjusted by writing to the apgain, cfnum and cfden registerssee energy to frequency conversion section . pin configuration top view (not to scale) ade7759 reset din dv dd dout av dd sclk v1p cs v1n clkout v2n clkin v2p irq agnd sag ref in/out zx dgnd cf 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10
rev. 0 ade7759 C8C pin no. mnemonic description 12 zx voltage waveform (channel 2) zero crossing output. this output toggles logic high and low at the zero crossing of the differential signal on channel 2see zero crossing detection section. 13 sag this open drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (channel 2) is crossed for a specified duration. see line voltage sag detec- tion section . 14 irq interrupt request output. this is an active low open drain logic output. maskable interrupts include active energy register rollover, active energy register at half-full, zero crossing, sag , and arrivals of new waveform samplessee interrupts section. 15 clkin master clock for adcs and digital signal processing. an external clock can be provided at this logic input. alternatively, a parallel resonant at crystal can be connected across clkin and clkout to provide a clock source for the ade7759. the clock frequency for specified opera- tion is 3.579545 mhz. ceramic load capacitors of between 10 pf to 30 pf should be used with the gate oscillator circuit. refer to crystal manufacturers data sheet for load capacitance requirem ents. 16 clkout a crystal can be connected across this pin and clkin as described above to provide a clock source for the ade7759. the clkout pin can drive one cmos load when either an external clock is supplied at clkin or a crystal is being used. 17 cs chip select. part of the 4-wire spi serial interface. this active low logic input allows the ad e7759 to share the serial bus with several other devices. see serial interface section. 18 sclk serial clock input for the synchronous serial interface. all serial data transfers are synchronized to this clocksee serial interface section. the sclk has a schmitt-trigger input for use with a clock source that has a slow edge transition time, e.g., opto-isolator outputs. 19 dout data output for the serial interface. data is shifted out at this pin on the rising edge of sclk. this logic output is normally in a high impedance state unless it is driving data onto the serial data bussee serial interface section. 20 din data input for the serial interface. data is shifted in at this pin on the falling edge of sclksee serial interface section. terminology measurement error the error associated with the energy measurement made by the ade7759 is defined by the following formula: percentage error energy registered by the ade true energy true energy = 7759 C phase error between channels the digital integrator and the hpf1 (high-pass filter) in channel 1 have nonideal phase response. to offset this phase response and equalize the phase response between channels, two phase correction networks are placed in channel 1: one for the digital integrator and the other for the hpf1. each phase correction network corrects the phase response of the corresponding com- ponent and ensures a phase match between channel 1 (current) and channel 2 (voltage) to within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range 40 hz to 1 khz. power supply rejection this quantifies the ade7759 measurement error as a percent- age of reading when the power supplies are varied. for the ac psr measurement a reading at nominal supplies (5 v) is taken. a second reading is obtained with the same input signal levels when an ac (175 mv rms/120 hz) signal is intro- duced onto the supplies. any error introduced by this ac signal is expressed as a percentage of readingsee measurement error definition above. for the dc psr measurement a reading at nominal supplies (5 v) is taken. a second reading is obtained with the same input signal levels when the supplies are varied 5%. any error introduced is again expressed as a percentage of reading. adc offset error this refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd the adcs still see a dc analog input signal. the magnitude of the offset depends on the gain and input range selectionsee charac teristic curves. however, when hpf1 is switched on, the offset is removed from channel 1 (current) and the power calcu- lation is not affected by this offset. the offsets may be removed by performing an offset calibrationsee analog inputs section. gain error the gain error in the ade7759 adcs is defined as the differ ence between the measured adc output code (minus the offset) and the ideal output codesee channel 1 adc and channel 2 adc. it is measured for each of the input ranges on channel 1 (0.5 v, 0.25 v and 0.125 v). the difference is expressed as a percentage of the ideal code. gain error match the gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 (for each of the input ranges) and a gain of 2, 4, 8, or 16. it is expressed as a percentage of the output adc code obtained under a gain of 1. this gives the gain error observed when the gain selection is changed from 1 to 2, 4, 8, or 16. pin function descriptions (continued)
rev. 0 C9C ade7759 current ?a 0.5 error ?% 0.4 0.3 0.2 0.1 0.0 ?.1 ?.2 ?.3 ?.4 ?.5 0.01 0.1 1 10 100 full scale = 0.5v gain = 1 integrator off internal reference ?0 c, pf = 1 +25 c, pf = 1 +85 c, pf = 1 tpc 1. error as a % of reading (integrator off, power factor = 1, internal reference, gain = 1) current a 0.5 error % 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.01 0.1 1 10 100 40 c, pf = 1 +25 c, pf = 1 +85 c, pf = 1 full scale = 0.5v gain = 1 integrator off external reference tpc 2. error as a % of reading (integrator off, power factor = 1, external reference, gain = 1) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 4 integrator off internal reference 40 c, pf = 1 +25 c, pf = 1 +85 c, pf = 1 tpc 3. error as a % of reading (integrator off, power factor = 1, internal reference, gain = 4) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 1 integrator off internal reference 40 c, pf = 0.5 +25 c, pf = 1 +85 c, pf = 0.5 +25 c, pf = 0.5 tpc 4. error as a % of reading (integrator off, power factor = 0.5, internal reference, gain = 1) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 1 integrator off external reference 40 c, pf = 0.5 +25 c, pf = 1 +85 c, pf = 0.5 +25 c, pf = 0.5 tpc 5. error as a % of reading (integrator off, power factor = 0.5, external reference, gain = 1) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 4 integrator off internal reference 40 c, pf = 0.5 +25 c, pf = 1 +85 c, pf = 0.5 +25 c, pf = 0.5 tpc 6. error as a % of reading (integrator off, power factor = 0.5, internal reference, gain = 4) typical performance characteristics
rev. 0 ade7759 C10C current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 4 integrator off external reference 40 c, pf = 1 +25 c, pf = 1 +85 c, pf = 1 tpc 7. error as a % of reading (integrator off, power factor = 1, external reference, gain = 4) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 4 integrator on internal reference 40 c, pf = 1 +25 c, pf = 1 +85 c, pf = 1 tpc 8. error as a % of reading (integrator on, power factor = 1, internal reference, gain = 4) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 4 integrator on external reference 40 c, pf = 1 +25 c, pf = 1 +85 c, pf = 1 tpc 9. error as a % of reading (integrator on, power factor = 1, external reference, gain = 4) current a 0.5 0.01 error % 0.1 1 10 100 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 full scale = 0.5v gain = 4 integrator off external reference 40 c, pf = 0.5 +25 c, pf = 1 +85 c, pf = 0.5 +25 c, pf = 0.5 tpc 10. error as a % of reading (integrator off, power factor = 0.5, external reference, gain = 4) current a 1.5 0.01 error % 0.1 1 10 100 1.3 0.3 full scale = 0.5v gain = 4 integrator on internal reference 40 c, pf = 0.5 +25 c, pf = 1 +85 c, pf = 0.5 +25 c, pf = 0.5 0.5 0.1 1.1 0.9 0.7 0.5 0.3 0.1 tpc 11. error as a % of reading (integrator on, power factor = 0.5, internal reference, gain = 4) current a 0.01 0.1 1 10 100 full scale = 0.5v gain = 4 integrator on external reference 40 c, pf = 0.5 +25 c, pf = 1 +85 c, pf = 0.5 +25 c, pf = 0.5 1.5 error % 1.3 0.3 0.5 0.1 1.1 0.9 0.7 0.5 0.3 0.1 tpc 12. error as a % of reading (integrator on, power factor = 0.5, external reference, gain = 4)
rev. 0 ade7759 C11C gain (ch1) rb 1 4 10 2.5 v dd 10 f10 f 100nf 100nf avdd dvdd reset din dout sclk cs clkout clkin irq sag zx cf agnd dgnd v1p v1n v2n v2p ref in/out u1 ade7759 to spi bus (used only for calibration) 22pf 22pf y1 3.58mhz not connected u3 to frequency counter ps2501-1 i 1k 33nf 1k 33nf 1k 33nf 600k 110v 1k 33nf 10 f 100nf rb ct turn ratio = 1800:1 channel 2 gain = 1 test circuit 1. performance curve (integrator off) v dd 10 f10 f 100nf 100nf avdd dvdd reset din dout sclk cs clkout clkin irq sag zx cf agnd dgnd v1p v1n v2n v2p ref in/out u1 ade7759 to spi bus (used only for calibration) 22pf 22pf y1 3.58mhz not connected u3 ps2501-1 i di/dt current sensor 100 1k 33nf 33nf 100 1k 33nf 33nf 1k 33nf 600k 110v 1k 33nf 10 f 100nf channel 1 gain = 4 channel 2 gain = 1 to frequency counter test circuit 2. performance curve (integrator on) analog inputs the ade7759 has two fully differential voltage input channels. the maximum differential input voltage for input pairs v1p/v1n and v2p/v2n are 0.5 v. in addition, the maximum signal level on analog inputs for v1p/v1n and v2p/v2n are 0.5 v with respect to agnd. each analog input channel has a pga (programmable gain amplifier) with possible gain selections of 1, 2, 4, 8, and 16. the gain selections are made by writing to the gain register see figure 5. bits 0 to 2 select the gain for the pga in channel 1 and the gain selection for the pga in channel 2 is made via bits 5 to 7. figure 4 shows how a gain selection for channel 1 is made using the gain register. v1p v1n v in k v in + gain[7:0] gain (k) selection offset adjust ( 50mv) ch1os[7:0] bit 0 to 5: sign magnitude coded offset correction bit 6: not used bit 7: digital integrator (on = 1, off = 0; default on) figure 4. pga in channel 1 in addition to the pga, channel 1 also has a full-scale input range selection for the adc. the adc analog input range selection is also made using the gain registersee figure 2. as mentioned previously the maximum differential input voltage is 0.5 v. however, by using bits 3 and 4 in the gain register, the maximum adc input voltage can be set to 0.5 v, 0.25 v, or 0.125 v. this is achieved by adjusting the adc referencesee reference circuit section. table i summarizes the maximum differential input signal level on channel 1 for the various adc range and gain selections. table i. maximum input signal levels for channel 1 max signal adc input range selection channel 1 0.5 v 0.25 v 0.125 v 0.5 v gain = 1 0.25 v gain = 2 gain = 1 0.125 v gain = 4 gain = 2 gain = 1 0.0625 v gain = 8 gain = 4 gain = 2 0.0313 v gain = 16 gain = 8 gain = 4 0.0156 v gain = 16 gain = 8 0.00781 v gain = 16 gain register * channel 1 and channel 2 pga control 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 addr: 0ah * register contents show power-on defaults pga 2 gain select 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 pga 1 gain select 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 channel 1 full scale select 00 = 0.5v 01 = 0.25v 10 = 0.125v figure 5. analog gain register test circuits
rev. 0 ade7759 C12C it is also possible to adjust offset errors on channel 1 and channel 2 by writing to the offset correction registers (ch1os and ch2os respectively). these registers allow channel offsets in the range 24 mv to 50 mv (depending on the gain setting) to be removed. note that it is not necessary to perform an offset correction in an energy measurement application if hpf1 channel 1 is switched on. figure 6 shows the effect of offsets on the real power calcula- tion. as seen in figure 6, an offset on channel 1 and channel 2 will contribute a dc component after multiplication. since this dc component is extracted by lpf2 to generate the active (real) power information, the offsets will have contributed an error to the active power calculation. this problem is easily avoided by enabling hpf1 in channel 1. by removing the offset from at least one channel, no error component is generated at dc by the multiplication. error terms at cos( t) are removed by lpf2 and by integration of the active power signal in the active energy register (aenergy[39:0])see energy calculation section. dc component (including error term) is extracted by the lpf for real power calculation i os v v os i v os i os v i 2 0 2 figure 6. effect of channel offsets on the real power calculation the contents of the offset correction registers are 6-bit, sign, and magnitude coded. the weighting of the lsb size depends on the gain setting, i.e., 1, 2, 4, 8, or 16. table ii shows the correctable offset span for each of the gain settings and the lsb weight (mv) for the offset correction registers. the maximum value that can be written to the offset correction registers is 31 decimalsee figure 7. table ii. offset correction range gain correctable span lsb size 1 50 mv 1.61 mv/lsb 2 37 mv 1.19 mv/lsb 4 30 mv 0.97 mv/lsb 8 26 mv 0.84 mv/lsb 16 24 mv 0.77 mv/lsb figure 7 shows the relationship between the offset correction register contents and the offset (mv) on the analog inputs for a gain setting of one. in order to perform an offset adjustment, the analog inputs should be first connected to agnd, and there should be no signal on either channel 1 or channel 2. a read from channel 1 or channel 2 using the waveform register will give an indication of the offset in the channel. this offset can be canceled by writing an equal but opposite offset value to the relevant offset register. the offset correction can be confirmed by performing another read. note that when adjusting the offset of channel 1, the digital integrator and the hpf1 should be disabled. ch1os[5:0] sign + 5 bits +50mv offset adjust 3fh 00h 1fh 50mv 0mv sign + 5 bits 01,1111b 11,1111b figure 7. channel offset correction range (gain = 1) di/dt current sensor and digital integrator di/dt sensor detects changes in magnetic field caused by ac current. figure 8 shows the principle of a di/dt current sensor. magnetic field created by current (directly proportional to current) emf (electromotive force) induced by changes in magnetic flux density (di/dt) + figure 8. principle of a di/dt current sensor the flux density of a magnetic field induced by a current is d irectly proportional to the magnitude of the current. the changes in the magnetic flux density passing through a conductor loop generate an electromotive force (emf) between the two ends of the loop. the emf is a voltage signal that is proportional to the di/dt of the current. the voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. figure 9 shows the mutual inductance produces a di/dt signal at the output of the sensor. + mutual inductance m i(t) v = m di(t) dt figure 9. mutual inductance between the di/dt sensor and the current carrying conductor the current signal needs to be recovered from the di/dt signal before it can be used for active power calculation. an integrator is therefore necessary to restore the signal to its original form. the ade7759 has a built-in digital integrator to recover the current signal from the di/dt sensor. the digital integrator on channel 1 is switched on by default when the ade7759 is powered up. setting the msb of the ch1os register to 0 will turn off the integrator. figures 10 to 13 show the magnitude and phase response of the digital integrator.
rev. 0 ade7759 C13C frequency hz 30 10 1 gain db 20 10 0 10 20 30 40 50 60 10 2 10 3 10 4 figure 10. gain response of the digital integrator frequency hz 88.0 10 1 phase degrees 88.5 89.0 89.5 90.0 90.5 91.0 91.5 92.0 10 2 10 3 10 4 figure 11. phase response of the digital integrator frequency hz 0 6 40 70 45 gain db 50 55 60 65 1 2 3 4 5 figure 12. gain response of the digital integrator (40 hz to 70 hz) 90.020 89.985 89.990 89.995 90.000 90.005 90.010 frequency hz phase degrees 40 45 70 50 55 60 65 90.015 89.980 (
,% 3

5& > 0 >9 note that the integrator has a C20 db/dec attenuation and ap proxi- mately C90 phase shift. when combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. however, the di/dt sensor has a 20 db/dec gain associated with it, and generates significant high frequency noise. a more effective antialiasing filter is needed to avoid noise due to aliasingsee antialias filter section. when the digital integrator is switched off, the ade7759 can be used directly with a conventional current sensor such as current transformer (ct) or a low resistance current shunt. zero crossing detection the ade7759 has a zero crossing detection circuit on channel 2. this zero crossing is used to produce an external zero cross signal (zx) and it is also used in the calibration modesee energy calibration section. the zero crossing signal is also used to initiate a temperature measurement on the ade7759see temperature measurement section. figure 14 shows how the zero cross signal is generated from the output of lpf1. adc 2 reference 1 lpf1 f 3db = 156hz 63% to +63% fs pga2 1, 2, 4, 8, 16 {gain [7:5]} v2p v2n v2 zero cross zx to multiplier 21.04 @ 60hz 1.0 0.93 zx v2 lpf1 figure 14. zero cross detection on channel 2
rev. 0 ade7759 C14C the zx signal will go logic high on a positive going zero crossing and logic low on a negative going zero crossing on channel 2. the zero crossing signal zx is generated from the output of lpf1. lpf1 has a single pole at 156 hz (clkin = 3.579545 mhz). as a result there will be a phase lag between the analog input signal v2 and the output of lpf1. the phase response of this filter is shown in the channel 2 sampling section of this data sheet. the phase lag response of lpf1 results in a time delay of approximately 0.97 ms (@ 60 hz) between the zero crossing on the analog inputs of channel 2 and the rising or falling edge of zx. the zero crossing detection also has an associated time-out register, zxtout. this unsigned, 12-bit register is decremented 1 lsb every 128/clkin seconds. the register is reset to its user pro- grammed full-scale value every time a zero crossing on channel 2 is detected. the default power on value in this register is fffh. if the register decrements to zero before a zero crossing is detected and the dissag bit in the mode register is logic zero, the sag pin will go active low. the absence of a zero crossing is also indicated on the irq output if the sag enable bit in the inter- rupt enable register is set to logic 1. irrespective of the enable bit setting, the sag flag in the interrupt status register is always set when the zxtout register is decremented to zero see inter- rupts section. the zero cross timeout register can be written/read by the user and has an address of 0ehsee serial interface section. the resolution of the register is 128/clkin seconds per lsb. thus the maximum delay for an interrupt is 0.15 second (128/ clkin 2 12 ). line voltage sag detection in addition to the detection of the loss of the line voltage signal (zero crossing), the ade7759 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value, for a number of half cycles. this condition is illus- trated in figure 15. full scale saglvl [7:0] sag sag reset high when channel 2 exceeds saglvl [7:0] channel 2 sagcyc [7:0] = 06h 6 half cycles figure 15. sag detection figure 15 shows the line voltage fall below a threshold that is set in the sag level register (saglvl[7:0]) for nine half cycles. since the sag cycle register (sagcyc[7:0]) contains 06h, the sag pin will go active low at the end of the sixth half cycle for which the line voltage falls below the threshold, if the dissag bit in the mode register is logic zero. as is the case when zero crossings are no longer detected, the sag event is also recorded by setting the sag flag in the interrupt status register. if the sag enable bit is set to logic 1, the irq logic output will go active lowsee interrupts section. the sag pin will go logic high again when the absolute value of the signal on channel 2 exceeds the sag level set in the sag level register. this is shown in figure 15 when the sag pin goes high during the tenth half cycle from the time when the signal on channel 2 first dropped below the threshold level. sag level set the contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from lpf1, after it is shifted left by one bit. for example, the nominal maximum code from lpf1 with a full-scale signal on channel 2 is 257f6h or (0010, 0101, 0111, 1111, 0110b)see channel 2 sampling section. shifting one bit left will give 0100, 1010, 1111, 1110, 1100b or 4afech. therefore writing 4ah to the sag level register will put the sag detection level at full scale. writing 00h will put the sag detection level at zero. the sag level register is compared to the most significant byte of a waveform sample after the shift left, and detection is made when the contents of the sag level register are greater. power supply monitor the ade7759 also contains an on-chip power supply monitor. the analog supply (avdd) is continuously monitored by the ade7759. if the supply is less than 4 v 5%, the ade7759 will go into an inactive state, i.e., no energy will be accumulated when the supply voltage is below 4 v. this is useful to ensure correct device operation at power-up and during power-down. the power supply monitor has built-in hysteresis and filtering. this gives a high degree of immunity to false triggering due to noisy supplies. av dd 5v 4v 0v ade7759 power-on reset sag inactive active inactive time figure 16. on-chip power supply monitor as seen in figure 16, the trigger level is nominally set at 4 v. the tolerance on this trigger level is about 5%. the sag pin can also be used as a power supply monitor input to the mcu. the sag pin will go logic low when the ade7759 is reset. the power supply and decoupling for the part should be such that the ripple at av dd does not exceed 5 v 5% as specified for normal operation. bit 6 of the interrupt status register (status[7:0]) will be set to logic high upon power-up or every time the analog supply (av dd ) dips below the power supply monitor threshold (4 v 5%) and recovers. however, no interrupt can be generated because the corre- sponding bit (bit 6) in the interrupt enable register (irqen[7:0]) is not activesee interrupts section .
rev. 0 ade7759 C15C interrupts ade7759 interrupts are managed through the interrupt status register (status[7:0]) and the interrupt enable register (irqen[7:0]). when an interrupt event occurs in the ade7759, the corresponding flag in the status register is set to a logic 1 see interrupt status register. if the enable bit for this interrupt in the interrupt enable register is logic 1, then the irq logic output goes active low. the flag bits in the status register are set irre- spective of the state of the enable bits. in order to determine the source of the interrupt, the system master (mcu) should perform a read from the status register with reset (rstatus[7:0]). this is achieved by carrying out a read from address 05h. the irq output will go logic high on completion of the interrupt status register read commandsee interrupt timing section. when carrying out a read with reset, the ade7759 is designed to ensure that no interrupt events are missed. if an interrupt event occurs just as the status register is being read, the event will not be lost and the irq logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. see the following section for a more detailed descrip tion. using the ade7759 interrupts with an mcu figure 17 shows a timing diagram with a suggested implementa- tion of ade7759 interrupt management using an mcu. at time t 1 the irq line will go active low, indicating that one or more interrupt events have occurred in the ade7759. the irq logic output should be tied to a negative edge-triggered external inter- rupt on the mcu. on detection of the negative edge, the mcu should be configured to start executing its interrupt service routine (isr). on entering the isr, all interrupts should be disabled using the global interrupt enable bit. at this point the mcu external interrupt flag can be cleared to capture interrupt events that occur during the current isr. when the mcu interrupt flag is cleared, a read from the status register with reset is carried out. this will cause the irq line to be reset logic high (t 2 )see interrupt timing section. the sta- tus register contents are used to determine the source of the interrupt(s) and hence the appropriate action to be taken. if a subsequent interrupt event occurs during the isr, that event will be recorded by the mcu external interrupt flag being set again (t 3 ). on returning from the isr, the global interrupt mask will be cleared (same instruction cycle) and the external interrupt flag will cause the mcu to jump to its isr once again. this will ensure that the mcu does not miss any external interrupts. interrupt timing the serial interface section should be reviewed first, before the interrupt timing. as previously described, when the irq output goes low the mcu isr must read the interrupt status register to determine the source of the interrupt. when reading the status register contents, the irq output is set high on the last falling edge of sclk of the first byte transfer (read interrupt status register command). the irq output is held high until the last bit of the next 8-bit transfer is shifted out (interrupt status register contents)see figure 18. if an interrupt is pending at this time, the irq output will go low again. if no interrupt is pending, the irq output will stay high. irq global interrupt mask set clear mcu interrupt flag read status with reset (05h) isr action (based on status contents) isr return global interrupt mask reset mcu interrupt flag set jump to isr mcu program sequence t 3 t 2 t 1 jump to isr figure 17. interrupt management sclk din dout irq t 9 t 1 t 11 t 11 read status register command status register contents db7 cs 000 0 0101 db0 figure 18. interrupt timing
rev. 0 ade7759 C16C temperature measurement ade7759 also includes an on-chip temperature sensor. a tem- perature measurement can be made by setting bit 5 in the mode register. when bit 5 is set logic high in the mode register, the ade7759 will initiate a temperature measurement on the next zero crossing. when the zero crossing on channel 2 is detected, the voltage output from the temperature sensing circuit is con- nected to adc1 (channel 1) for digitizing. the resultant code is processed and placed in the temperature register (temp[7:0]) approximately 26 s later (24 clkin cycles). if enabled in the interrupt enable register (bit 5), the irq output will go active low when the temperature conversion is finished. please note that temperature conversion will introduce a small amount of noise in the energy calculation. if temperature conversion is performed frequently (i.e., multiple times per second), a noticeable error will accumulate in the resulting energy calculation over time. the contents of the temperature register are signed (twos complement) with a resolution of approximately 1 lsb/ c. the temperature register will produce a code of 00h when the ambient temperature is approximately 70 c. the temperature mea- surement is uncalibrated in the ade7759 and has an offset tolerance that could be as high as 20 c. analog-to-digital conversion the analog-to-digital conversion in the ade7759 is carried out using two second order sigma-delta adcs. the block diagram in figure 19 shows a first order (for simplicity) sigma-delta adc. the converter is made up of two parts, first the sigma-delta modulator and second the digital low-pass filter. a sigma-delta modulator converts the input signal into a con- tinuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the ade7759, the sampling clock is equal to clkin/4. the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and therefore the bitstream) will approach that of the input signal level. for any given input value in a single sam- pling interval, the data from the 1-bit adc is virtually m eaningless. only when a large number of samples are averaged will a mean ingful result be obtained. this averaging is carried out in the second part of the adc, the digital low-pass filter. by averaging a large number of bits from the modulator, the low-pass filter can pro duce 20-bit data words that are proportional to the input signal level. 1 20 digital low-pass filter r c analog low-pass filter + v ref 1-bit dac mclk/4 latched comparator .....10100101..... + figure 19. first order sigma-delta ( - ? ) adc the sigma-delta converter uses two techniques to achieve high resolution from what is essentially a one-bit conversion tech nique. the first is oversampling. by oversampling we mean that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. for example, the sampling rate in the ade7759 is clkin/4 (894 khz) and the band of interest is 40 hz to 2 khz. oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandw idth. with the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is loweredsee figure 20. however, oversampling alone is not an efficient enough method to improve the signal to noise ratio (snr) in the band of interest. for example, an oversampling ratio of 4 is required just to increase the snr by only 6 db (one bit). to keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. this is what happens in the sigma-delta modulator: the noise is shaped by the integrator, which has a high-pass type response for the quantization noise. the result is that most of the noise is at the higher frequencies, where it can be removed by the digital low-pass filter. this noise shaping is also shown in figure 20. 447 0 894 2 noise signal digital filter antialias filter (rc) shaped noise sampling frequency 447 0 894 2 noise signal high resolution output from digital lpf frequency khz frequency khz figure 20. noise reduction due to oversampling and noise shaping in the analog modulator antialias filter figure 20 also shows an analog low-pass filter (rc) on the input to the modulator. this filter is present to prevent aliasing. aliasing is an artifact of all sampled systems. basically it means that frequency components in the input signal to the adc that are higher than half the sampling rate of the adc will appear in the sampled signal at a frequency below half the sampling rate. figure 21 illustrates the effect. frequency components (arrows shown in black) above half the sampling frequency (also known as the nyquist frequency, i.e., 447 khz) get imaged or folded back down below 447 khz (arrows shown in grey). this will happen with all adcs regardless of the architecture. in the example shown, it can be seen that only frequencies near the sampling frequency (894 khz) will move into the band of interest for metering, i.e., 40 hzC2 khz. this allows us to use a very simple lpf (low-pass filter) to attenuate these high frequencies (near 900 khz) and to prevent distortion in the band of interest. for a conventional current sensor, a simple rc filter (single pole) with a corner frequency of 10 khz will produce an attenuation of approximately 40 dbs at 894 khzsee figure 20. the 20 db per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensor.
rev. 0 ade7759 C17C image frequencies sampling frequency aliasing effects 0 2 447 894 frequency khz figure 21. adc and signal processing in channel 1 for a di/dt sensor such as a rogowski coil, however, the sensor has 20 db per decade gain. this will neutralize the C20 db per decade attenuation produced by this simple lpf and nullifies the antialias filter. therefore, when using a di/dt sensor, measure should be taken to offset the 20 db per decade gain coming from the di/dt sensor and produce sufficient attenuation to eliminate any aliasing effect. one simple approach is to cascade two rc filters to produce C40 db per decade attenuation. the transfer function for a cascaded filter is the following: hs sr c sr c sr c s r c r c () = ++ + + 1 1112212 1122 2 where r 1 c 1 represents the rc used in the first stage of the cascade and r 2 c 2 in that of the second stage. the s 2 term in the transfer function produces a C40 db/decade attenuation. note that to minimize the measurement error, especially at low power factor, it is important to match the phase angle between the voltage and the current channel. the small phase mismatch in the exter- nal antialias filter can be corrected using the phase calibra tion register (phcal[7:0])see phase compensation section . adc transfer function below is an expression which relates the output of the lpf in the sigma-delta adc to the analog input signal level. both adcs in the ade7759 are designed to produce the same out- put code for the same input signal level. code adc v v in ref (). , = 3 0492 262 144 therefore, with a full-scale signal on the input of 0.5 v and an internal reference of 2.42 v, the adc output code is nominally 165,151 or 2851fh. the maximum code from the adc is 262,144, which is equivalent to an input signal level of 0.794 v. however, for specified performance it is not recommended that the full-scale input signal level of 0.5 v be exceeded. reference circuit shown in figure 22 is a simplified version of the reference out- put circuitry. the nominal reference voltage at the ref in/out pin is 2.42 v. this is the reference voltage used for the adcs in the ade7759. however, channel 1 has three input range selec- tions, which are selected by dividing down the reference value used for the adc in channel 1. the reference value used for channel 1 is divided down to 1/2 and 1/4 of the nominal value by using an internal resistor divider as shown in figure 22. 60 a ptat 2.5v 1.7k 12.5k 12.5k 12.5k 12.5k ref in/out 2.42v maximum load = 10 a output impedance 6k reference input to adc channel 1 (range select) 2.42v, 1.21v, 0.6v figure 22. adc and reference circuit output the ref in/out pin can be overdriven by an external source, e.g., an external 2.5 v reference. note that the nominal refer- ence value supplied to the adcs is now 2.5 v not 2.42 v. this has the effect of increasing the nominal analog input signal range by 2.5/2.42 100% = 3%, or from 0.5 v to 0.5165 v. the internal voltage reference on the ade7759 has a tempera- ture drift associated with itsee ade7759 specifications for the temperature coefficient specification (in ppm c). the value of the temperature drift varies slightly from part to part. since the reference is used for the adcs in both channel 1 and 2, any x% drift in the reference will result in 2x% deviation of the meter reading. the reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. however, if guaranteed temperature performance is needed, one needs to use an exter- nal voltage reference. alternatively, the meter can be calibrated at multiple temperatures. real-time compensation can be achieved easily using the on-chip temperature sensor. channel 1 adc figure 23 shows the adc and signal processing chain for chan- nel 1. in waveform sampling mode the adc outputs a signed twos complement 20-bit data word at a maximum of 27.9 ksps (clkin/128). the output of the adc can be scaled by 50% to perform an overall power calibration or to calibrate the adc output. while the adc outputs a 20-bit twos complement value, the maximum full-scale positive value from the adc is limited to 40,000h (+262,144 decimal). the maximum full-scale nega tive value is limited to c0000h (C262,144 decimal). if the analog inputs are over-ranged, the adc output code will clamp at these values. with the specified full-scale analog input signal of 0.5 v (or 0.25 v or 0.125 vsee analog inputs section) the adc will produce an output code that is approximately 63% of its full-scale value. this is illustrated in figure 23. the diagram in figure 23 shows a full-scale voltage signal being applied to the differential inputs v1p and v1n. the adc output swings bet ween d7ae1h (C165,151) and 2851fh (+165,151). this is approxim ately 63% of the full-scale value 40,000h (262,144). o ver-ranging the analog inputs with more than 0.5 v differential (0.25 or 0.125, depending on channel 1 full-scale selection) will cause the adc output to increase towards its full-scale value. however, for speci- fied operation the differential signal on the analog inputs should not exceed the recommended value of 0.5 v.
rev. 0 ade7759 C18C channel 1 adc gain adjust the adc gain in channel 1 can be adjusted by using the multi plier and active power gain register (apgain[11:0]). the gain of the adc is adjusted by writing a twos complement 12- bit word to the active power gain register. below is the expression that shows how the gain adjustment is related to the contents of the active power gain register. code adc apgain =+ ? ? ? ? ? ? ? ? ? ? ? ? 1 2 12 for example, when 7ffh is written to the active power gain register the adc output is scaled up by 50%. 7ffh = 2047 decimal, 2047/2 12 = 0.5. similarly, 801h = 2047 decimal (signed twos complement) and adc output is scaled by C50%. these two examples are graphically illustrated in figure 23. channel 1 sampling the waveform samples may also be routed to the waveform register (mode[14:13] = 1, 0) to be read by the system master (mcu). in waveform sampling mode the wsmp bit (bit 3) in the interrupt enable register must also be set to logic 1. the active power and energy calculation will remain uninterrupted during waveform sampling. when in waveform sample mode, one of four output sample rates may be chosen by using bits 11 and 12 of the mode regis- ter (wavsel1, 0). the output sample rate may be 27.9 ksps, 14 ksps, 7 ksps, or 3.5 kspssee mode register section. the interrupt request output irq signals a new sample availability by going active low. the timing is shown in figure 24. the 20-bit wave form samples are transferred from the ade7759 one byte (eight-bits) at a time, with the most significant byte shifted out first. the 20-bit data word is right justified and sign extended to 24 bits (three bytes)see serial interface section. read from waveform sign channel 1 data 20 bits sampling rate (27.9ksps, 14ksps, 7ksps, or 3.5ksps) 0 16 s irq sclk din dout 0 0 01 hex figure 24. waveform sampling channel 1 channel 1 and channel 2 waveform sampling mode in channel 1 and channel 2 waveform sampling mode (mode[14:13] = 01), the output is a 40-bit waveform sample data that contains both the waveform samples from channel 1 and channel 2 adcs. figure 25 shows the format of the 40-bit waveform output. ch2[19:16] ch1[19:16] ch1[15:0] ch2[15:0] 1 byte 2 bytes 2 bytes bit 39 bit 0 figure 25. 40-bit combined channel 1 and channel 2 waveform sample data format adc 1 hpf reference 2.42v, 1.21v, 0.6v v1 0v analog input range 0.5v, 0.25v, 0.125v, 62.5mv, 31.3mv, 15.6mv, 00000h 40000h c0000h 2851fh d7ae1h +fs fs +63% fs 63% fs adc output word range 00000h 2851fh +63% fs 63% fs d7ae1h +94.5% fs +31.5% fs 31.5% fs 94.5% fs 3c7aeh 1428fh ebd71h c3852h apgain[11:0] 000h 7ffh 801h channel 1 (active power) data range to multiplier to waveform sample register sinc 3 digital lpf 00000h 1ef74h +63% fs 63% fs e108ch +94.5% fs +31.5% fs 31.5% fs 94.5% fs 2e72eh f7bah f0846h d18d2h apgain[11:0] 000h 7ffh 801h channel 1 (active power) data range after integrator (50hz) digital integrator * 00000h 19ce0h +63% fs 63% fs e6320h +94.5% fs +31.5% fs 31.5% fs 94.5% fs 26b50h 0ce70h f3190h d94b0h apgain[11:0] 000h 7ffh 801h channel 1 (active power) data range after integrator (60hz) 50hz 60hz v1p v1n pga1 v1 multiplier {gain[4:3]} {gain[2:0]} 1, 2, 4, 8, 16 801hex 7ffhex apgain[11:0] * when digital integrator is enabled, full-scale output data varies depending on the signal frequency because of 20db/decade frequency response. figure 23. adc and signal processing in channel 1
rev. 0 ade7759 C19C channel 2 adc channel 2 sampling in channel 2 waveform sampling mode (mode[14:13] = 1, 1 and wsmp = 1) the adc output code scaling for channel 2 is the same as channel 1, i.e., the output swings between d7ae1h (C165,151) and 2851fh (+165,151)see adc channel 1 section. however, before being passed to the waveform register, the adc output is passed through a single-pole, low-pass filter with a cutoff frequency of 156 hz. the plots in figure 26 show the magnitude and phase response of this filter. frequency hz 0 10 1 phase degrees 20 40 60 80 10 2 10 3 0 20 gain db 60hz, 0.6db 60hz, 21.04 10 figure 26. magnitude and phase response of lpf1 the lpf1 has the effect of attenuating the signal. for example, if the line frequency is 60 hz, the signal at the output of lpf1 will be attenuated by 7%. hf hz hz db () . C. = + ? ? ? ? ? ? == 1 1 60 156 093 06 2 note that lpf1 does not affect the power calculation. the signal processing chain in channel 2 is illustrated in figure 27. unlike channel 1, channel 2 has only one analog input range (0.5 v differential). however, like channel 1, channel 2 does have a pga with gain selections of 1, 2, 4, 8, and 16. for energy measurem ent, the output of the adc is passed directly to the multiplier and is not filtered. an hpf is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation. when in waveform sample mode, one of four output sample rates can be chosen by using bits 11 and 12 of the mode register. the available output sample rates are 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps see mode register section. the interrupt request output irq signals a new sample availability by going active low. the timing is the same as that for channel 1 and is shown in figure 24. adc 2 v1 0v analog input range 0.5v, 0.25v, 0.125v, 62.5mv, 31.25mv reference 1 20 to waveform register lpf1 63% to +63% fs to multiplier pga2 1, 2, 4, 8, 16 {gain [7:5]} v2p v2n v2 2.42v 40000h 2851fh 257f6h 00000h da80ah d7ae1h c0000h lpf output word range +fs +63% fs +59% fs 59% fs 63% fs fs figure 27. adc and signal processing in channel 2 phase compensation when the hpf is disabled, the phase error between channel 1 and channel 2 is zero from dc to 3.5 khz. when hpf1 is enabled, channel 1 has a phase response illustrated in figures 29 and 30. also shown in figure 31 is the magnitude response of the filter. as can be seen from the plots, the phase response is almost zero from 45 hz to 1 khz. this is all that is required in typical energy measurement applications. however, despite being internally phase compensated, the ade7759 must work with transducers that may have inherent phase errors. for example, a phase error of 0.1 to 0.3 is not uncommon for a ct (current transformer). these phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. the errors associated with phase mismatch are particularly noticeable at low power factors. the ade7759 provides a means of digitally calibrating these small phase errors. the ade7759 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for small phase errors. because the compensation is in time, this technique should only be used for small phase errors in the range of 0.1 to 0.5 . correcting large phase errors using a time shift technique can introduce signifi- cant phase errors at higher harmonics. the phase calibration register (phcal[7:0]) is a twos comple- ment signed single byte register that has values ranging from 9eh (C98 in decimal) to 5ch (92 in decimal). by changing the phcal register, the time delay in the channel 2 signal path can change from C110 s to +103 s (clkin = 3.579545 mhz). one lsb is equivalent to 1.12 s time delay or advance. with a line fre- quency of 60 hz, this gives a phase resolution of 0.024 at the fundamental (i.e., 360 1.12 s 60 hz). figure 28 illustrates how the phase compensation is used to remove a 0.1 phase lead in channel 1 due to the external transducer. in order to cancel the lead (0.1 ) in channel 1, a phase lead must also be intro- duced into channel 2. the resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.024 . the phase lead is achieved by introducing a time advance into channel 2. a time advance of 4.48 s is made by writing C4 (fch) to the time delay block, thus reducing the amount of time delay by 4.48 s, or equivalently, a phase lead of approximately 0.1 at line frequency of 60 hz.
rev. 0 ade7759 C20C 0 0 1 1 1 1 1 1 70 1 pga1 v1p v1n v1 adc 1 hpf 20 pga2 v2p v2n v2 adc 2 delay block 1.12 s/lsb 20 lpf2 v2 v1 60hz 0.1 v1 v2 channel 2 delay reduced by 4.48 s (0.1 lead at 60hz) fch in phcal [7:0] phcal [7:0] 110 s to +103 s 60hz figure 28. phase calibration frequency hz 0.30 100 phase degrees 0.25 0.20 0.15 0.10 0.05 0.00 0.05 0.10 200 300 400 500 600 700 800 900 1000 figure 29. combined phase response of the hpf and phase compensation (10 hz to 1 khz) frequency hz 0.30 40 phase degrees 0.25 0.20 0.15 0.10 0.05 0.00 0.05 0.10 45 50 55 60 65 70 figure 30. combined phase response of the hpf and phase compensation (40 hz to 70 hz) frequency hz 0.4 error % 54 56 58 60 62 64 66 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 figure 31. combined gain response of the hpf and phase compensation (deviation of gain in % from gain at 60 hz) active power calculation electrical power is defined as the rate of energy flow from source to load. it is given by the product of the voltage and current waveforms. the resulting waveform is called the instantaneous power signal, and it is equal to the rate of energy flow at every instant of time. the unit of power is the watt or joules/second equation 3 gives an expression for the instantaneous power signal in an ac system. vt v t () ( ) = 2 (1) it i t ( ) sin( ) = 2 (2) where v = rms voltage, i = rms current. pt vt it p t vi vi t () () () ( ) C cos( ) = = 2 (3) the average power over an integral number of line cycles (n) is given by the expression in equation 4. p nt ptdt vi nt == 1 0 () (4) where t is the line cycle period. p is referred to as the active or real power. note that the active power is equal to the dc com- ponent of the instantaneous power signal p(t) in equation 3, i.e., vi. this is the relationship used to calculate active power in the ade7759. the instantaneous power signal p(t) is generated by multiplying the current and voltage signals. the dc component of the instantaneous power signal is then extracted by lpf2 (low-pass filter) to obtain the active power information. this process is illustrated graphically in figure 32. since lpf2 does not have an ideal brick wall frequency re sponse (see figure 33), the active power signal will have some ripple due to the instanta- neous power signal. this ripple is sinusoidal and has a frequency equal to twice the line frequency. since the ripple is sinusoidal in nature it will be removed when the active power signal is integrated to calculate energysee energy calculation section.
rev. 0 ade7759 C21C instantaneous power signal p(t) = v i v i cos(2 t) active real power signal = v i 1999ah vi cccdh 00000h current i(t) = 2 i sin( t) vo ltag e v(t) = 2 v sin( t) figure 32. active power calculation frequency hz 24 1 db 20 3 10 30 100 12 16 8 4 0 figure 33. frequency response of lpf2 figure 34 shows the signal processing chain for the active power calculation in the ade7759. as explained, the active power is calculated by low pass filtering the instantaneous power signal. 1 20 lpf2 v i cccdh 1999ah 1999ah 00h instantaneous power signal p(t) 40% to +40% fs active power signal p current signal i(t) hpf voltage signal v(t) multiplier figure 34. active power signal processing shown in figure 35 is the maximum code (hexadecimal) output range for the active power signal (lpf2) when the digital inte- grator is disabled. note that when the integrator is enabled, the output range changes depending on the input signal frequency. furthermore, the output range can also be changed by the active power gain registersee channel 1 adc section. the minimum output range is given when the active power gain register con- tents are equal to 800h, and the maximum range is given by w riting 7ffh to the active power gain register. this can be used to calibrate the active power (or energy) calculation in the ade7759. +30% fs +20% fs +10% fs 10% fs 20% fs 30% fs 13333h cccdh 6666h f999ah f3333h ecccdh 00000h output lpf2 positive power negative power 000h 7ffh 800h {apgain [11:0]} channel 1 (active power) calibration range figure 35. active power calculation output range energy calculation as stated earlier, power is defined as the rate of energy flow. this relationship can be expressed mathematically as: p de dt = (5) where p = power and e = energy conversely, energy is given as the integral of power: e pdt = (6) the ad7759 achieves the integration of the active power signal by continuously accumulating the active power signal in the 40- bit active energy register (asenergy[39:0]). this discrete time accumulation or summation is equivalent to integration in continuous time. equation 7 expresses this relationship. e p t dt lim p nt t t n = = ? ? ? ? ? ? = () ( ) 0 0 (7) where n is the discrete time sample number and t is the sample period. the discrete time sample period (t) for the accumulation regis- ter in the ade7759 is 1.1 s (4/clkin). as well as calculating the energy, this integration removes any sinusodial components which may be in the active power signal. figure 36 shows a graphical representation of this discrete time integration or accumulation. the active power signal in the waveform register is continuously added to the active energy register. this addition is a signed addition; therefore negative energy will be subtracted from the active energy contents. as shown in figure 36, the active power signal is accumulated in a 40-bit signed register (aenergy[39:0]). the active power signal can be read from the waveform register by setting mode[14:13] = 0, 0 and setting the wsmp bit (bit 3) in the interrupt enable register to 1. like channel 1 and channel 2 waveform sampling modes, the waveform data is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 kspssee figure 24. figure 37 shows this energy accumulation for full- scale signals (sinusodial) on analog inputs. the three curves displayed illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 7ffh, 000h, and 800h. the active power gain register is used to carry out power calibration in the ade7759.
rev. 0 ade7759 C22C as shown, the fastest integration time will occur when the active power gain register is set to maximum full scale, i.e., 7ffh. 7f,ffff,ffffh 3f,ffff,ffffh 00,0000,0000h 40,0000,0000 80,0000,0000h aenergy [39:0] 5.8s 11.5s 23s time sec apgain = 7ffh apgain = 000h apgain = 800h figure 37. energy register rollover time for full-scale power (minimum and maximum power gain) note that the energy register contents will roll over to full-scale negative (80,0000,0000h) and continue increasing in value when the power or energy flow is positivesee figure 37. conversely, if the power is negative, the energy register would underflow to full-scale positive (7f, ffff, ffffh) and continue decreasing in value. by using the interrupt enable register, the ade7759 can be configured to issue an interrupt ( irq ) when the active energy register is half-full (positive or negative) or when an over/underflow occurs. integration time under steady load as mentioned in the last section, the discrete time sample period (t) for the accumulation register is 1.1 s (4/clkin). with full-scale sinusoidal signals on the analog inputs, digital integrator turned off, and the active power gain register set to 000h, the average word value from lpf2 is cccdsee figures 34 and 35. the maximum value that can be stored in the active energy register before it overflows is 2 39 or 7f,ffff,ffffh. therefore the integration time under these conditions is calculated as follows: time f ffff ffffh cccdh s onds == 7 1 1 11 53 ,, .. sec power offset calibration the ade7759 also incorporates an active power offset register (apos[15:0]). this is a signed twos complement 16-bit register that can be used to remove offsets in the active power calcula tion see figure 36. an offset may exist in the power calculation due to crosstalk between channels on the pcb or in the ic itself. the offset calibration will allow the contents of the active power register to be maintained at zero when no power is being consumed. two hundred fifty-six lsbs (apos = 0100h) written to the active power offset register are equivalent to 1 lsb in the waveform sample register. assuming the average value outputs from lpf2 to store in the waveform register is cccdh (52,429 in decimal) when inputs on channels 1 and 2 are both at full scale and the digital integrator is turned off. at C60 db down on channel 1 (1/ 1000 of the channel 1 full-scale input), the average word value outputs from lpf2 is 52.429 (52,429/1,000). one lsb in the waveform register has a measurement error of 1/52.429 100% = 1.9% of the average value. the active power offset register has a resolu tion equal to 1/256 lsb of the waveform register, hence the power offset correction resolution is 0.007%/lsb (1.9%/256) at C60 db. when the digital integrator is turned on, the resolution of the lsb varies slightly with the line frequency. energy-to-frequency conversion ade7759 also provides energy to frequency conversion for cali- bration purposes. after initial calibration at manufacturing, the manufacturer or end customer will often verify the energy meter calibration. one convenient way to verify the meter calibration is for the manufacturer to provide an output frequency that is pro- portional to the energy or active power under steady load conditions. this output frequency can provide a simple, single-wire, optically sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 15 0 apos [15:0] lpf2 20 current channel voltage channel output lpf2 time nt 4 clkin t waveform register values active power signal = p + + + + waveform [24:0] aenergy [39:0] waveform register values are accumulated (integrated) in the active energy register 23 0 39 0 figure 36. energy calculation
rev. 0 ade7759 C23C isolated interface to external calibration equipment. figure 38 illustrates the energy-to-frequency conversion in the ade7759. the energy-to-frequency conversion is accomplished by accumu- lating the active power signal in a 24-bit register. an output pulse is generated when there is a zero to one transition on the msb (most significant bit) of the register. under steady load conditions the output frequency is proportional to the active power. the output frequency at cf, with full-scale ac signals on channel 1 and chan- nel 2 and cfden = 000h, cfnum = 000h, and apgain = 000h, is approximately 5.593 khz. this can be calculated as follows: with the active power gain register set to 000h, the average value of the instantaneous power signal (output of lpf2) is cccdh or 52,429 decimal. an output frequency is generated on cf when the msb in the energy to frequency register (24 bits) toggles, i.e., when the register accumulates 2 23 . this means the register is updated 2 23 /cccdh times (or 159.999 times). since the update rate is 4/clkin or 1.1175 s, the time between msb toggles (cf pulses) is given as: 159 999 1 1175 1 78799 10 5592 86 4 .. . (.) C = sshz equation 8 gives an expression for the output frequency at the energy-to-frequency (etf) output with the contents of cfden and cfnum registers are both zero. etf output hz average lpf output clkin () = 2 2 25 (8) this output frequency is easily scaled by a pair of calibration frequency divider registers (cfden[11:0] and cfnum[11:0]). these frequency scaling registers are 12-bit registers that can scale the output frequency by 1 to 2 12 . the output frequency is given by the expression below. cf hz etf output hz cfnum cfden () () [:] [:] = + + 11 0 1 11 0 1 (9) for example, if the cf output frequency is 5.59286 khz while the contents of cfnum and cfden are zero, the cf output frequency can be set to 25 hz by writing 8 bdh (2237 in decimal) to the cfden register and 00ah (10 in decimal) to the cfnum register. note that the cfnum and cfden registers are meant only to scale down the frequency from the etf output. therefore, the content of cfden should always be set no less than that of the cfnum register, i.e., the maximum output frequency from cf pin will never exceed that of the etf output. the power-up default value for cfden is 3fh and cfnum is 0h. the output frequency will have a slight ripple at a frequency equal to twice the line frequency. this is due to imperfect filtering of the instantaneous power signal to generate the active power signalsee active power calculation section. equation 3 gives an expression for the instantaneous power signal. this is filtered by lpf2, which has a magnitude response given by equation 10. hf fhz () /. = + 1 189 (10) the active power signal (output of lpf2) can be rewritten as pt vi vi fhz ft l l () /. cos =? + ? ? ? ? ? ? () 12 89 4 (11) where fl is the line frequency (e.g., 60 hz) from equation 6 e t vit vi ffhz ft ll l () /. sin =? + () ? ? ? ? ? ? ? ? ? ? () 41289 4 (12) from equation 12 it can be seen that there is a small ripple in the energy calculation due to a sin(2 t) component. this is shown graphically in figure 39. the active energy calculation is shown by the dashed straight line and is equal to v i t. the sinusoidal ripple in the active energy calculation is also shown. since the average value of a sinusoid is zero, this ripple will not contribute to the energy calculation over time. however, the ripple can be observed in the frequency output, especially at higher output frequencies. the ripple will get larger as a percentage of the fre- quency at larger loads and higher output frequencies. the reason is that at higher output frequencies the integration or averaging time in the energy-to-frequency conversion process is shorter. as a consequence, some of the sinusoidal ripple is observable in the frequency output. choosing a lower output frequency at cf for calibration can significantly reduce the ripple. also averaging the output frequency by using a longer gate time for the counter will achieve the same results. sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 15 0 apos [15:0] lpf2 20 + + + + waveform [23:0] energy-to-frequency 23 0 23 0 msb transition cf active power offset calibration 11 0 cfden [11:0] 11 0 cfnum [11:0] active power signal p figure 38. energy-to-frequency conversion
rev. 0 ade7759 C24C 4 l (1 + 2 l /8.9hz) vi sin(4 l t ) e(t) vlt figure 39. output frequency ripple line cycle energy accumulation mode in line cycle energy accumulation mode, the energy accumu- lation of the ade7759 can be synchronized to the channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. the advantage of summing the active energy over an integer number of half-line cycles is that the sinusoidal component in the active energy is reduced to zero. this eliminates any ripple in the energy calculation. energy is calcu- lated more accurately and in a shorter time because integration period can be shortened. by using the line cycle energy accu- mulation mode, the energy calibration can be greatly simp lified and the time required to calibrate the meter can be significantly reduced. the ade7759 is placed in line cycle e nergy accu- mulation mode by setting bit 7 (cycmode) in the mode register. in line cycle energy accumulation mode the ade7759 accu mulates the active power signal in the lenergy register (address 14h) for an integral number of half cycles, as shown in figure 40. the number of half-line cycles is specified in the linecyc register (address 14h). the ade7759 can acc umu- late active power for up to 16,383 half cycles. because the active power is integrated on an integral number of half-line cycles, at the end of a line cycle energy accumulation cycle, the cycend flag in the interrupt status register is set (bit 2). if the cycend enable bit in the interrupt enable register is enabled, the irq output will also go active low. thus the irq line can also be used to signal the completion of the line cycle energy accumulation. another calibration cycle will start as long as the cycmode bit in the mode register is set. note that the result of the first calibration is invalid and should be ignored. the result of all subsequent line cycle accumulation is correct. from equations 5 and 11. e t vidt vi ffhz wt dt o nt ll o nt () C /. () = + () ? ? ? ? ? ? ? ? ? ? 41289 2 cos (13) where n is an integer and t is the line cycle period. since the sinusoidal component is integrated over an integer number of line cycles, its value is always zero. therefore: e t vidt o nt () = + 0 (14) e t vint () = (15) note that in this mode, the 14-bit linecyc register can hold a maximum value of 16,383. in other words, the line cycle en ergy accumulation mode can be used to accumulate active energy for a maximum duration over 16,383 half-line cycles. at 60 hz line frequency, it translates to a total duration of 16,383/120 hz = 136.5 seconds. the 40-bit signed lenergy register can overflow if large signals are present at the inputs. the lenergy register can only hold up to 11.53 seconds of active energy when both its input channels are at ac full-scalesee integration time under steady load section. large linecyc content is meant to be used only when the input signal is low and extensive averaging is required to reduce the noise. calibrating the energy meter calculating the average active power when calibrating the ade7759, the first step is to calibrate the frequency on cf to some required meter constant, e.g., 3200 imp/kwh. to determine the output frequency on cf, the average value of the active power signal (output of lpf2) must first be deter- mined. one convenient way to do this is to use the line cycle energy accumulation mode. when the cycmode (bit 7) bit in the mode register is set to a logic 1, energy is accumu lated over an integer number of half-line cycles as described in the last section. since the line frequency is fixed at, say, 60 hz, and the number of half cycles of integration is specified, the total integration time is given as: 1 260 hz number of half cycles sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 15 0 apos [15:0] lpf2 + + + + waveform [23:0] lenergy [39:0] 39 0 23 0 linecyc [13:0] active power signal p cccdh 00h from multiplier lpf1 channel 2 adc zero cross detect calibration control figure 40. energy calculation in line cycle energy accumulation mode
rev. 0 ade7759 C25C for 255 half cycles this would give a total integration time of 2.125 seconds. this would mean the energy register was updated 2.125/1.1175 s (4/clkin) times. the average output value of lpf2 is given as: contents of lenergy at the end number of times lenergy was updated [:] [:] 39 0 39 0 or, equivalently, in terms of contents of various ade7759 registers and clkin and line frequencies ( f l ): average word lpf lenergy f linecyc clkin l () [:] [:] 2 39 0 8 13 0 = (16) where f l is the line frequency. calibrating the frequency at cf once the average active power signal is calculated it can be used to determine the frequency at cf before calibration. when the frequency before calibration is known, the pair of cf frequency divider registers (cfnum and cfden) can be adjusted so as to produce the required frequency on cf. in this example a meter constant of 3200 imp/kwh is chosen as an appropriate constant. this means that under a steady load of 1 kw, the output frequency on cf would be: frequency cf imp kwh hz () / . = == 3200 60 60 3200 3600 0 8888 min sec assuming the meter is set up with a test current (basic current) of 20 a and a line voltage of 220 v for calibration, the load is cal- culated as 220 v 20 a = 4.4 kw. therefore, the expected output frequency on cf under this steady load condition would be 4.4 0.8888 hz = 3.9111 hz. under these load conditions the transducers on channel 1 and channel 2 should be selected such that the signal on the voltage channel should see approximately half scale and the signal on the current channel about 1/8 of full scale (assuming a maximum current of 80 a). the average value from lpf2 is calculated as 3,276.81 decimal using the calibration mode as described above. then using equation 8 (energy to fre- quency conversion), the frequency under this load is calculated as: frequency cf mhz hz () .. . = = 3276 81 3 579545 2 349 566 25 this is the frequency with the contents of the cfnum and cfden registers equal to 000h. the desired frequency out is 3.9111 hz. therefore, the cf frequency must be divided by 349.566/3.9111 hz or 89.3779 decimal. this is achieved by loading the pair of cf divider registers with the closest rational number. in this case the closest rational number is found to be 25/2234 (or 19h/8bah). therefore, 18h and 8b9h should be written to the cfnum and cfden registers respectively. note that the cf frequency is divided by the contents of (cfnum + 1)/(cfden + 1). with the cf divide registers contents equal to 18h/8b9h, the output frequency is given as 349.566 hz / 89.36 = 3.91188 hz. note that this setting has an error of +0.02%. calibrating cf is made easy by using the line cycle energy accumulation mode on the ade7759 provided that the line frequency is accurately known during calibration. using line cycle energy accumulation mode, the calibration time can be reduced by synchronizing energy accumulation to the zero cross- ing of the voltage channel. see line cycle energy accumulation mode section. however, this requires the line frequency to be precisely known. as shown in equation 16, the average value of lpf2 is directly proportional to the line frequency. any deviation from the nominal frequency will directly affect the calibration result. the line frequency could be measured using the zx output of the ade7759. alternatively, the average value of lpf2 can be calculated from the output frequency from cfsee energy to frequency conversion section. note that besides cfnum and cfden registers, changing apgain[11:0] register will also affect the output frequency from cf. the apgain register has a resolution of 0.0244%/lsb. energy meter display besides the pulse output, which is used to verify calibration, a solid state energy meter will very often require some form of display. the display should show the amount of energy consumed in kwh (killowatt hours). one convenient and simple way to interface the ade7759 to a display or energy register (e.g., mcu with nonvolatile memory) is to use cf. for example the cf frequency could be calibrated to 1,000 imp/kwhr. the mcu would count pulses from cf. every pulse would be equivalent to 1 watt-hour. if more resolution is required, the cf frequency could be set to, say, 10,000 imp/kwh. if more flexibility is required when monitoring energy usage, the active energy register (aenergy) can be used to calculate energy. a full description of this register can be found in the energy calculation section. the aenergy register gives the user both sign and magnitude information regarding energy consumption. on completion of the cf frequency output cali- bration, i.e., after the active power gain (apgain) register has been adjusted, a second calibration sequence can be initiated. the purpose of this second calibration routine is to determine a kwh/lsb coefficient for the aenergy register. once the coefficient has been calculated, the mcu can determine the energy consumption at any time by reading the aenergy contents and multiplying by the coefficient to calculate kwh. clkin frequency in this data sheet, the characteristics of the ade7759 are shown with the clkin frequency equal to 3.579545 mhz. however, the ade7759 is designed to have the same accuracy at any clkin frequency within the specified range. if the clkin frequency is not 3.579545 mhz, various timing and filter charac- teristics will need to be redefined with the new clkin frequency. for example, the cutoff frequencies of all digital filters (lpf1, lpf2, hpf1, etc.) will shift in proportion to the change in clkin frequency according to the following equation: new frequency original frequency clkin frequency mhz = 3 579545 . (17) the change of clkin frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (sclk). but one needs to observe the read/write timing of the serial data transfersee timing characteristics. table iii lists various timing changes that are affected by clkin frequency.
rev. 0 ade7759 C26C table iii. frequency dependencies of the ade7759 parameters parameter clkin dependency nyquist frequency for ch 1 and 2 adcs clkin/8 phcal resolution (seconds per lsb) 4/clkin active energy register update rate (hz) clkin/4 waveform sampling rate (number of samples per second) wavsel 1, 0 = 0 0 clkin/128 0 1 clkin/256 1 0 clkin/512 1 1 clkin/1024 maximum zxtout period 524,288/clkin suspending the ade7759 functionality the analog and the digital circuit can be suspended separately. the analog portion of the ade7759 can be suspended by setting the asuspend bit (bit 4) of the mode register to logic high see mode register. in suspend mode, all waveform samples from the adcs will be set to zeros. the digital circuitry can be halted by stopping the clkin input and maintaining a logic high or low on clkin pin. the ade7759 can be reactivated by restoring the clkin input and setting the asuspend bit to logic low. application information application note an-564 contains detailed information on how to design a ansi class 100 watt-hour meter based on the ade7756, a pin-to-pin compatible product with the ade7759. application note an-578 describes an algorithm on how to calculate the voltage and current rms values using an external mcu. it is available from the ade7756 product homepage under the application note link on the energy metering homepage, www.analog.com/energymeter. serial interface all ade7759 functionality is accessible via several on-chip registerssee figure 41. the contents of these registers can be updated or read using the on-chip serial interface. after power-on or toggling the reset pin low or a falling edge on cs , the ade7759 is placed in communications mode. in communica tions mode the ade7759 expects a write to its communications register. the data written to the communications register determines whether the next data transfer operation will be a read or a write and also which register is accessed. therefore, all data transfer operations with the ade7759, whether a read or a write, must begin with a write to the communications register. communications register in out in out in out in out in out register #1 register #2 register #3 register #n 1 register #n register address decode din dout figure 41. addressing ade7759 registers via the communications register the communications register is an 8-bit wide register. the msb determines whether the next data transfer operation is a read or a write. the five lsbs contain the address of the register to be accessed. see communications register section for a more detailed description. figure 42 and figure 43 show the data transfer sequences for a read and write operation, respectively. on completion of a data transfer (read or write) the ade7759 once again enters communications mode. din sclk cs dout communications register write multibyte read data address 0 0 0 figure 42. reading data from the ade7759 via the serial interface din sclk cs communications register write address 0 0 1 multibyte write data figure 43. writing data to the ade7759 via the serial interface a data transfer is complete when the lsb of the ade7759 register being addressed (for a write or a read) is transferred to or from the ade7759. the serial interface of the ade7759 is made up of four signals: sclk, din, dout and cs . the serial clock for a data transfer is applied at the sclk logic input. this logic input has a schmitt- trigger input structure, which allows slow rising (and falling) clock edges to be used. all data transfer operations are synchro- nized to the serial clock. data is shifted into the ade7759 at the din logic input on the falling edge of sclk. data is shifted out of the ade7759 at the dout logic output on a rising edge of sclk. the cs logic input is the chip select input. this input is used when multiple devices share the serial bus. a falling edge on cs also resets the serial interface and places the ade7759 in communications mode. the cs input should be driven low for the entire data transfer operation. bringing cs high during a data transfer operation will abort the transfer and place the serial bus in a high impedance state. the cs logic input may be tied low if the ade7759 is the only device on the serial bus. however with cs tied low, all initiated data transfer operations must be fully com- pleted, i.e., the lsb of each register must be transferred as there is no other way of bringing the ade7759 back into communications mode without resetting the entire device, i.e., using reset . serial write operation the serial write sequence takes place as follows. with the ade7759 in communications mode (i.e., the cs input logic low), a write to the communications register first takes place. the msb of this byte transfer is a 1, indicating that the data transfer operation is a write. the lsbs of this byte contain the address of the register to be written to. the ade7759 starts shifting in the register data on the next falling edge of sclk. all remaining bits of register data are shifted in on the falling edge of subsequent sclk pulsessee figure 44.
rev. 0 ade7759 C27C din sclk cs t 2 t 3 t 1 t 4 t 5 t 7 t 6 t 8 command byte most significant byte least significant byte 1 00 a4 a3 a2 a1 a0 db7 db0 db7 db0 t 7 figure 44. serial interface write timing diagram sclk din x x x x db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 most significant byte least significant byte figure 45. 12-bit serial write operation command byte most significant byte least significant byte sclk cs t 1 t 10 t 13 t 9 0 00 a4 a3 a2 a1 a0 db0 db7 db0 db7 din dout t 11 t 11 t 12 figure 46. serial interface read timing diagram as explained earlier, the data write is initiated by a write to the communications register followed by the data. during a data write operation to the ade7759, data is transferred to all on- chip registers one byte at a time. after a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ade7759 on-chip registers. although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer should not finish until at least 4 s after the end of the previous byte transfer. this functionality is expressed in the timing speci- fication t 6 see figure 44. if a write operation is aborted during a byte transfer ( cs brought high), then that byte will not be written to the destination register. destination registers may be up to 3 bytes widesee register description section. hence the first byte shifted into the serial port at din is transferred to the msb (most significant byte) of the destination register. if the addressed register is 12 bits wide, for example, a two-byte data transfer must take place. the data is always assumed to be right justified: therefore in this case, the four msbs of the first byte would be ignored and the four lsbs of the first byte written to the ade7759 would be the four msbs of the 12-bit word. figure 45 illustrates this example. serial read operation during a data read operation from the ade7759, data is shifted out at the dout logic output on the rising edge of sclk. as was the case with the data write operation, a data read must be preceded with a write to the communications register. with the ade7759 in communications mode (i.e., cs logic low), an 8-bit write to the communications register first takes place. the msb of this byte transfer is a 0, indicating that the next data transfer operation is a read. the lsbs of this byte contain the address of the register that is to be read. the ade7759 starts shifting out of the register data on the next rising edge of sclk see figure 46. at this point the dout logic output leaves its high impedance state and starts driving the data bus. all remain- ing bits of register data are shifted out on subsequent sclk rising edges. the serial interface also enters communications mode again as soon as the read has been completed. at this point the dout logic output enters a high impedance state on the falling edge of the last sclk pulse. the read operation may be aborted by bringing the cs logic input high before the data transfer is complete. the dout output enters a high imped- ance state on the rising edge of cs . when an ade7759 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. this allows the ade7759 to modify its on-chip registers without the risk of corrupting data during a multi byte transfer. note when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 4 s after the end of the write operation. if the read command is sent within 4 s of the write operation, the last byte of the write operation may be lost. this timing constraint is given as timing specification t 9.
rev. 0 ade7759 C28C table iv. register list address name r/w # of bits default description 01h waveform r 24/40 0h the waveform register is a read-only register. this register contains the sampled waveform data from channel 1, channel 2, or the active power signal. the data source and the length of the waveform regis- ters are selected by data bits 14 and 13 in the mode registersee channel 1 and 2 sampling section. 02h aenergy r 40 0h the active energy register. active power is accumulated (integrated) over time in this 40-bit, read-only register. the energy register can hold a minimum of 11.53 seconds of active energy information with full- scale analog inputs before it overflowssee energy calculation section. 03h rstenergy r 40 0h same as the active energy register except that the register is reset to 0 following a read operation. 04h status r 8 40h interrupt status register. this is an 8-bit read-only register. the status register contains information regarding the source of ade7759 inter- ruptssee interrupts section. 05h rststatus r 8 0h same as the interrupt status register except that the register contents are reset to 0 (all flags cleared) after a read operation. 06h mode r/w 16 000ch the mode register. this is a 16-bit register through which most of the ade7759 functionality is accessed. signal sample rates, filter enabling and calibration modes are selected by writing to this register. the contents may be read at any timesee mode register section. 07h cfden r/w 12 3fh cf frequency divider denominator register. the output frequency on the cf pin is adjusted by writing to this 12-bit read/write register see energy-to-frequency conversion section. 08h ch1os r/w 8 80h channel 1 offset adjust. the msb is used to enable the digital integra- tor. bit 6 is not used. writing to bit 0 to 5 allows offsets on channel 1 to be removedsee analog inputs section and ch1os register section. 09h ch2os r/w 6 0h channel 2 offset adjust. writing to this 6-bit register allows any offsets on channel 2 to be removedsee analog inputs section. 0ah gain r/w 8 0h pga gain adjust. this 8-bit register is used to adjust the gain selec- tion for the pga in channel 1 and 2see analog inputs section. 0bh apgain r/w 12 0h active power gain adjust. this is a 12-bit register. the active power calculation can be calibrated by writing to this register. the calibration range is 50% of the nominal full-scale active power. the resolution of the gain adjust is 0.0244%/lsbsee channel 1 adc gain adjust section. 0ch phcal r/w 8 0h phase calibration register. the phase relationship between channel 1 and channel 2 can be adjusted by writing to this 8-bit register. the valid content of this twos complement register is between 9eh and 5ch, which is a phase difference of C2.365 to +2.221 at 60 hz in 0.0241 stepssee phase compensation section. 0dh apos r/w 16 0h active power offset correction. this 16-bit register allows small off- sets in the active power calculation to be removedsee active power calculation section. checksum register the ade7759 has a checksum register (chksum[5:0]) to ensure the data bits received in the last serial read operation are not corrupted. the 6-bit checksum register is reset before the first bit (msb of the register to be read) is put on the dout pin. during a serial read operation, when each data bit becomes available on the rising edge of sclk, the bit will be added to the checksum register. in the end of the serial read operation, the content of the checksum register will be the sum of all the ones contained in the register previously read. using the checksum register, the user can determine if an error has occurred during the last read operation. note that a read to the chksum register will also generate a checksum of the chksum register itself. content of register (n-bytes) checksum register addr: 1eh + + dout figure 47. checksum register for serial interface read
rev. 0 ade7759 C29C address name r/w # of bits default description 0eh zxtout r/w 12 fffh zero cross timeout. if no zero crossings are detected on channel 2 within a time period specified by this 12-bit register, the interrupt request line ( irq ) will be activated. the maximum timeout period is 0.15 secondsee zero crossing detection section. 0fh sagcyc r/w 8 ffh sag line cycle register. this 8-bit register specifies the number of consecutive half-line cycles the signal on channel 2 must be below saglvl before the sag output is activatedsee voltage sag detec- tion section. 10h irqen r/w 8 40h interrupt enable register. ade7759 interrupts may be deactivated at any time by setting the corresponding bit in this 8-bit enable register to logic 0. the status register will continue to register an interrupt event even if disabled. however, the irq output will not be activatedsee interrupts section. 11h saglvl r/w 8 0h sag voltage level. an 8-bit write to this register determines at what peak signal level on channel 2 the sag pin will become active. the signal must remain low for the number of cycles specified in the sagcyc register before the sag pin is activatedsee line voltage sag detection section. 12h temp r 8 0h temperature register. this is an 8-bit register which contains the result of the latest temperature conversionsee temperature measurement section. 13h linecyc r/w 14 3fffh line cycle energy accumulation mode half-cycle register. this 14- bit register is used during line cycle energy accumulation mode to set the number of half-line cycles active energy is accumulatedsee line cycle energy accumulation mode section. 14h lenergy r 40 0h line cycle energy accumulation mode active energy register. this 40-bit register accumulates active energy during line cycle energy accumulation mode. the number of half-line cycles is set by the linecyc registersee line cycle energy accumulation mode section. 15h cfnum r/w 12 0h cf frequency divider numerator register. the output frequency on the cf pin is adjusted by writing to this 12-bit read/write registersee energy to frequency conversion section . 1eh chksum r 6 0h checksum register. this 6-bit read-only register is equal to the sum of all the ones in the previous readsee serial read operation section . 1fh dierev r 8 01h die revision register. this 8-bit read-only register contains the revision number of the silicon. register descriptions all ade7759 functionality is accessed via the on-chip registers. each register is accessed by first writing to the communicatio ns register and then transferring the register data. a full description of the serial interface protocol is given in the serial in terface section of this data sheet. communications register the communications register is an 8-bit, write-only register that controls the serial data transfer between the ade7759 and the host processor. all data transfer operations must begin with a write to the communications register. the data written to the communi ca- tions register determines whether the next operation is a read or a write and which register is being accessed. table v outline s the bit designations for the communications register.
rev. 0 ade7759 C30C bit bit location mnemonic description 0 to 4 a0 to a4 the five lsbs of the communications register specify the register for the data transfer operation. table iii lists the address of each ade7759 on-chip register. 5 to 6 reserved these bits are unused and should be set to zero. 7w/ r when this bit is a logic 1, the data transfer operation immediately following the write to the communications register will be interpreted as a write to the ade7759. when this bit is a logic 0 the data transfer operation immediately following the write to the communications register will be interpreted as a read operation. mode register (06h) the ade7759 functionality is configured by writing to the mode registersee figure 45. table vi summarizes the functionality of each bit in the mode register. table vi. mode register bit bit location mnemonic description 0 dishpf the hfp (high-pass filter) in channel 1 is disabled when this bit is set. 1 dislpf2 the lpf (low-pass filter) after the multiplier (lpf2) is disabled when this bit is set. 2 discf the frequency output cf is disabled when this bit is set. 3 dissag the line voltage sag detection is disabled when this bit is set. 4 asuspend by setting this bit to logic 1, both ade7759s a/d converters can be turned off. in normal opera- tion, this bit should be left at logic 0. all digital functionality can be stopped by suspending the clock signal at clkin pin. 5 tempsel the temperature conversion starts when this bit is set to 1. this bit is automatically reset to 0 when the temperature conversion is finished. 6 swrst software chip reset. a data transfer should not take place to the ade7759 for at least 18 s after a software reset. 7 cycmode setting this bit to logic 1, places the chip in line cycle energy accumulation mode. 8 disch1 adc 1 (channel 1) inputs are internally shorted together. 9 disch2 adc 2 (channel 2) inputs are internally shorted together. 10 swap by setting this bit to logic 1 the analog inputs v2p and v2n are connected to adc 1 and the analog inputs v1p and v1n are connected to adc 2. 12, 11 dtrt1, 0 these bits are used to select the waveform register update rate. dtrt 1 dtrt0 update rate 0 0 27.9 ksps (clkin/128) 0 1 14 ksps (clkin/256) 1 0 7 ksps (clkin/512) 1 1 3.5 ksps (clkin/1024) 14, 13 wavsel1, 0 these bits are used to select the source of the sampled data for the waveform register. wavsel1, 0 length source 0 0 24 bits active power signal (output of lpf2) 0 1 40 bits channel 1 and channel 2 1 0 24 bits channel 1 1 1 24 bits channel 2 15 test1 writing a logic 1 to this bit position places the ade7759 in test mode. this is intended for factory testing only and should be left at 0. table v. communications register db7 db6 db5 db4 db3 db2 db1 db0 w/ r 0 0 a4 a3 a2 a1 a0
rev. 0 ade7759 C31C 0000000000001100 1514131211109876543210 addr: 06h dishpf (disable hpf1 in channel 1) dislpf2 (disable lpf2 after multiplier) discf (disable frequency output cf) dissag (disable sag output) asuspend (suspend ch1 and ch2 adc s) stemp (start temperature sensing) swrst (software chip reset) cycmode (line cycle energy accumulation mode) test1 (test mode selection should be set to 0) wavsel (waveform selection for sample mode) 00 = lpf2 01 = ch1 + ch2 (40-bit waveform samples) 10 = ch1 11 = ch2 dtrt (waveform samples output data rate) 00 = 27.9ksps (clkin/128) 01 = 14.4ksps (clkin/256) 10 = 7.2ksps (clkin/512) 11 = 3.6ksps (clkin/1024) swap (swap ch1 and ch2 adcs) disch2 (short the analog inputs on channel 2) disch1 (short the analog inputs on channel 1) note: register contents show power-on defaults figure 48. mode register interrupt status register (04h)/reset interrupt status register (05h) the status register is used by the mcu to determine the source of an interrupt request ( irq ). when an interrupt event occurs in the ade7759, the corresponding flag in the interrupt status register is set logic high. if the enable bit for this flag is logic 1 in the inter- rupt enable register, the irq logic output goes active low. when the mcu services the interrupt, it must first carry out a read from the interrupt status register to determine the source of the interrupt. table vii. interrupt status register, reset interrupt status register, and interrupt enable register bit interrupt location flag description 0 aehf indicates that an interrupt was caused by the 0 to 1 transition of the msb of the active energy register. 1 sag indicates that an interrupt was caused by a sag on the line voltage or no zero crossings were detected. 2 cycend indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the linecyc registersee line cycle energy accumulation mode section . 3 wsmp indicates that new data is present in the waveform register. 4 zx this status bit reflects the status of the zx logic ouputsee zero crossing detection section. 5 temp indicates that a temperature conversion result is available in the temperature register. 6 reset indicates the end of a reset (for both software or hardware reset). the corresponding enable bit has no function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot be enabled to cause an interrupt. 7 aeof indicates that the active energy register has overflowed. 01000000 76543210 addr: 04h/reset: 05h aehf (active energy register half full) sag (line voltage sag detect) cycend (line cycle energy accumulation end) wsmp (waveform sampling) aeof (active energy register overflow) temp (temperature register ready) zx (zero crossing detected) reset (end of a hardware or software reset) note: register contents show power on defaults figure 49. interrupt status register
rev. 0 C32C c02744C0C10/01(0) printed in u.s.a. ade7759 outline dimensions dimensions shown in inches and (mm). 20-shrink small outline package (rs-20) 0.037 (0.94) 0.022 (0.559) 0.009 (0.229) 0.005 (0.127) 8 0 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 20 11 10 1 pin 1 0.0256 (0.65) bsc 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.078 (1.98) 0.068 (1.73) seating plane controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design 00000000 76543210 addr: 10h aehf (active energy register half full) sag (line voltage sag detect) cycend (end of line cycle energy accumulation) wsmp (waveform sampling) aeof (active energy register overflow) not used temp (temperature register ready) zx (zero crossing detected) note: register contents show power on defaults figure 50. interrupt enable register ch1os register (08h) the ch1os register is an 8-bit, read/write enabled register. the msb of this register is used to switch on/off the digital inte grator in channel 1, and bits 0 to 5 indicate the amount of the offset correction in channel 1. table viii summarizes the function of thi s register. table viii. ch1os register bit location bit mnemonic description 0 to 5 offset the six lsbs of the ch1os register control the amount of dc offset correction in channel 1 adc. the 6-bit offset correction is sign and magnitude coded. bits 0 to 4 indicate the magnitude of the offset correction. bit 5 shows the sign of the offset correction. a 0 in bit 5 means the offset correction is positive and a 1 indicates the offset correction is negative. 6 not used this bit is unused. 7 integrator this bit is used to activate the digital integrator on channel 1. the digital integrator is switched on by setting this bit. this bit is set to be 1 on default. 10000000 76543210 addr: 08h ch1os register * sign and magnitude coded offset correction bits digital integrator selection 1 = enable 0 = disable not used * register contents show power-on default figure 51. ch1os register

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